Design of Low Power Clock Gated Sense Amplifier Flip Flop With SVL Circuit

Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption in VLSI circuits. In this paper, a dualedge triggered flip-flop with high performance and clock gated sense amplifier flip-flop is designed. Moreover, the pulse generator can be shared among many flip-flops to reduce the power dissipation and chip area. By incorporating the Dual-Edge Triggering Mechanism in the new fast latch the DET-SAFF is able to achieve low-power consumption. But it has small delay. To further reduce the power consumption and delay at low switching activities, a Clock-Gated Sense-Amplifier (CG-SAFF) is engaged. The proposed CG-SAFF demonstrates its advantage in terms of power reduction. Switching activity, CG-SAFF can realize maximum power saving. On the other hand, the speed remained almost constantly with a minimal overhead in terms of the switching the input signal by adding“Selfcontrollable Voltage Level (SVL)” Circuit. The result of the simulation demonstrates that this clock gated sense amplifier flip-flop with SVL Circuit is a viable means to improve design performance, operating speed and achieve the greater power efficiency. KeywordsClock-gated, High-performance, low-power sense-amplifier flip-flop, Self-controllable Voltage Level (SVL)